An
Efficient Constant Multiplier Architecture
Based
on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for
Reconfigurable FIR Filter Synthesis
VLSI PROJECT-------IEEE-2015
This project proposes a
VHBCSE algorithm for designing a reconfigurable FIR filter. To design an
efficient reconfigurable FIR filter, according to the proposed VHBCSE algorithm,
2-bit binary common sub-expression elimination (BCSE) algorithm has been
applied vertically across adjacent coefficients on the 2-D space of the
coefficient matrix initially, followed by applying variable-bit BCSE algorithm
horizontally within each coefficient.
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