A PFD and Charge Pump Switching Circuit to Optimize the Output Phase Noise of the PLL in 90 nm CMOS

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VLSI BACKEND PROJECT ----- IEEE-2015

This project presents the design of a novel Phase Frequency Detector (PFD) and Charge Pump (CP) switching circuits for the frequency synthesizer in phase-locked loop (PLL). Our proposed PFD technique can eliminate the effect of missing edge and phase ambiguity problems in conventional PFDs circuit. Also, a novel CP circuit with a special switching scheme has been incorporated to reduce the current mismatch error and charge injection error problem with this new design technique.