An Area- and Energy-Efficient FIFO Design Using Error-Reduced Data Compression and

Near-Threshold Operation for Image/Video Applications

IEEE TRANSACTION---VLSI---2015

In this project, we propose an area- and energy-efficient FIFO

design. On architecture level, a technique named as FIFOwith error-reduced data compression (FERDC) is proposedto reduce the FIFO size. This reduces both area and powerconsumption of the FIFO with negligible distortion.


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