Aging-Aware Reliable Multiplier Design With
Adaptive Hold Logic
VLSI FRONT END PROJECT-----IEEE-2015
It is important to design reliable high-performance multipliers. In this project, we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect.
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Adaptive Hold Logic
VLSI FRONT END PROJECT-----IEEE-2015
It is important to design reliable high-performance multipliers. In this project, we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect.
DOWNLOAD BASEPAPER
DOWNLOAD ABSTRACT
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